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Avoiding and Identifying False Sharing Among Threads (PDF 218KB)Abstract In symmetric multiprocessor (SMP) systems, each processor has a local cache. False sharing occurs when threads on different processors modify variables that reside on the same cache line.
This invalidates the cache line and forces an update, which hurts performance.
The source line shown in red in the following example code causes false sharing: (the source line shown in red), which invalidates the cache line for all processors. False sharing occurs when threads on different processors modify variables that reside on the same cache line.
This invalidates the cache line and forces a memory update to maintain cache coherency.
If the processor sees the same cache line which is now marked ‘M’ being accessed by another processor, the processor stores the cache line back to memory and marks its cache line as ‘Shared’.
The other processor that is accessing the same cache line incurs a cache miss.
Background False sharing is a well-known performance issue on SMP systems, where each processor has a local cache.
It occurs when threads on different processors modify variables that reside on the same cache line, as illustrated in Figure 1.
False sharing increases this coordination and can significantly degrade application performance.
On first load of a cache line, the processor will mark the cache line as ‘Exclusive’ access.
As long as the cache line is marked exclusive, subsequent loads are free to use the existing data in cache.
This circumstance is called false sharing because each thread is not actually sharing access to the same variable.
Access to the same variable, or true sharing, would require programmatic synchronization constructs to ensure ordered data access.Since compilers are aware of false sharing, they do a good job of eliminating instances where it could occur.For example, when the above code is compiled with optimization options, the compiler eliminates false sharing using thread-private temporal variables.In Figure 1, threads 0 and 1 require variables that are adjacent in memory and reside on the same cache line.